Conventionally, a power on reset (POR) circuit is used to generate a power on reset signal for a power supply chip and to trigger a power up read signal which is for reading status bits in order to obtain the current status information of the power supply chip. A system wide reboot could be triggered after the bias voltage (Vcc) of the power supply chip drops to an operating voltage that is below a predetermined Vcc operating voltage but above the ground voltage. The POR circuit is used by a power supply chip which normally is not allowed to consume current while the power supply chip is in a standby mode, but a power drop may nevertheless occur while the power supply chip is in the standby mode. Since characteristics of a realistic power supply chip may not match the characteristics of an ideal power supply chip, the POR mechanism might not function as intended.
FIG. 1A illustrates triggering of an POR signal of an ideal POR circuit. According to FIG. 1, it is assumed that the lowest Vcc operating voltage level 111 is predetermined and is shown as the dotted line. As the Vcc voltage ramps up, when Vcc voltage reaches the lowest Vcc operating voltage level 111 at a first time point 101, a POR will occur at the first time point 101. When the Vcc operating voltage drops below the lowest Vcc operating voltage level 111 at a second time point 102, the power supply chip will set the POR circuit to be ready for a POR. When the Vcc operating voltage goes back up and exceeds the lowest Vcc operating voltage at a third time point 103, the POR will occur at the third time point. However, a realistic POR circuit might not match such characteristics.
FIG. 1B shows the characteristics of a real POR signal generated by a typical POR circuit of a power supply chip. It is assumed that the lowest Vcc operation voltage level 111 is predetermined and is shown as the dotted line. Realistically, it might be possible that the POR reset voltage at the fourth time point 104 is actually lower than the lowest Vcc operation voltage level 111. Also, the Vcc might not drop low enough in order for the POR circuit to be set for a POR. Such problem is further described in FIG. 1C.
Referring to FIG. 1C, it is assumed that the lowest Vcc operating voltage level is predetermined and is shown as the dotted line. As the Vcc voltage ramps up, when Vcc voltage exceeds the lowest Vcc operating voltage level 111 at a fifth time point 105, a POR will occur around the first time point 105, but the voltage at which the POR occur might be lower than the lowest Vcc operating voltage level 111. When the Vcc operating voltage drops below the lowest Vcc operating voltage at a sixth time point 106, the power supply chip will set the POR circuit to be ready for a POR. When the Vcc operating voltage goes back up and exceeds the lowest Vcc operating voltage at a seventh time point 107, the POR will occur around the seventh time point. However, the power supply chip setting the POR circuit to be ready for a POR at the sixth time point 106 might not actually happen because realistically, the Vcc operating voltage might not drop far enough below the lowest Vcc operating voltage level 111. As such, the POR around the seventh time point also would not occur.
The above described problems could be summarized as follows. First, it is not easy to have the Vcc operating voltage exactly meeting the intended voltage in order for the POR to occur. Second, the Vcc operating voltage might not drop far enough below the lowest Vcc operating voltage level. Third, it is not easy to design the POR circuit because the POR circuit should consume just about no current when the power supply chip is at a standby mode. Based on the above considerations, the POR circuit may still require improvements.